The exemplary embodiments of this invention relate generally to semiconductor devices and, more specifically, to structures and methods relating to self-aligned contacts with replacement metal gates to inhibit or at least reduce contact resistance variation between semiconductor devices.
In the manufacture of an integrated circuit (IC) chip, various semiconductor devices (e.g., field effect transistors such as metal oxide semiconductor field effect transistors (MOSFETs)) can be fabricated on a supporting substrate using various deposition techniques. Current flows within a semiconductor device from a source to a drain. A gate generates an electric field that controls the current flow. Precise alignment of the connections or contacts to the semiconductor device with regard to the source, drain, and gate is not always possible, particularly as trends in semiconductor fabrication progress toward further size reduction.
As further size reduction leads to shrinking dimensions in gate length, it should be realized that there is also limited space in which to land contacts in the source and drain regions of a semiconductor device. This leads to a desire to utilize a self-aligned contact (SAC) configuration. In a SAC configuration used with a MOSFET, for example, the gate is engineered such that source/drain contacts land in their intended places so as not to result in a shorted device or otherwise interfere with the operation of the device. However, in a SAC configuration, when such a contact moves over a spacer and gate of a device (due to overlay and alignment variability in the fabrication process), the area of active contact between the SAC and the source/drain region changes. This can result in variations in the contact resistance of the semiconductor device both within and from wafer to wafer and can affect the net drive current that can be expected from the device. Such large variations in contact resistances between devices are generally not tolerable.